1. Field of the Invention
The present invention relates to a via and a method of forming the via and, more particularly, to a via and a method of forming the via with a substantially planar top surface.
2. Description of the Related Art
A via is a well-known metal structure that touches and extends vertically up from the top surface of a silicon region, a silicided region, or a metal trace to touch the bottom surface of an overlying metal trace in a metal interconnect structure. Vias which touch the top surface of a silicon region or a silicided region are also known as contacts.
FIGS. 1A-1D show cross-sectional views that illustrate a prior art method of forming a via. As shown in FIG. 1A, the method utilizes a conventionally-formed semiconductor wafer 100 that includes a conductive structure 110 which is formed in a semiconductor structure 112, and a non-conductive structure 114 that touches and overlies conductive structure 110 and semiconductor structure 112. Conductive structure 110 can represent a silicon region, such as a source or drain region, a silicided region formed on silicon or polysilicon, or a metal trace.
As further shown in FIG. 1A, the method begins by forming a patterned photoresist layer 120 on the top surface of non-conductive structure 114. The patterned photoresist layer 120 is formed in conventional manner, which includes depositing a layer of photoresist, projecting a light through a patterned black/clear glass plate known as a mask to form a patterned image on the layer of photoresist to soften the photoresist regions exposed by the light, and removing the softened photoresist regions to expose regions on the top surface of non-conductive structure 114. (Only one exposed region is shown for clarity.)
As shown in FIG. 1B, after patterned photoresist layer 120 has been formed, the exposed region of non-conductive structure 114 is etched to form an opening 122 that exposes the top surface of conductive structure 110. Following the formation of opening 122, patterned photoresist layer 120 is removed.
As shown in FIG. 1C, once patterned photoresist layer 120 has been removed, a titanium/titanium nitride layer 124 is conformally deposited on non-conductive structure 114 to line opening 122 and touch the top surface of conductive structure 110. Following this, a tungsten layer 126 is conformally deposited on titanium/titanium nitride layer 124 to fill opening 122. Titanium/titanium nitride layer 124 and tungsten layer 126 are deposited in a conventional manner, such as by using chemical vapor deposition, plasma vapor deposition, or atomic layer deposition.
As further shown in FIG. 1C, the deposition of tungsten layer 126 forms a seam 130 that extends vertically into the center of opening 122. As tungsten is deposited, the width of opening 122 becomes smaller and smaller until the tungsten on the side wall of opening 122 meets in the center of opening 122 to fill opening 122. Seam 130, in turn, represents the point where the tungsten meets in the center of opening 122.
As shown in FIG. 1D, after tungsten layer 126 has been deposited, tungsten layer 126 and titanium/titanium nitride layer 124 are removed using conventional chemical-mechanical polishing to expose the top surface of non-conductive structure 114, and form a via 132 that includes the remaining portions of titanium/titanium nitride layer 124 and tungsten layer 126.
One problem with conventional chemical-mechanical polishing, commonly known as coring, is that the chemical used in the polishing frequently attacks seam 130 and forms a cavity 134 as further shown in FIG. 1D. During the formation of a conventional metal interconnect structure, a layer of metal is deposited on non-conductive structure 114 and via 132 as part of the process for forming a metal trace. The deposited layer of metal, in turn, fills up cavity 134 in via 132. Thus, in a conventional metal interconnect process, cavity 134 presents no significant issue.
However, when a metal interconnect structure includes a carbon nanotube switch, where the switch is closed by extending down to touch the top surface of via 132, the presence of cavity 134 can prevent the carbon nanotube switch from making a predictable and reliable electrical connection with the top surface of via 132.
FIGS. 2A-2C show cross-sectional views that illustrate examples of a prior-art carbon nanotube switch 200. As shown in FIGS. 2A-2C, switch 200 includes a conductive structure 210 that is formed in a semiconductor structure 212, a non-conductive structure 214 that touches and overlies conductive structure 210 and semiconductor structure 212, and a via 216 that extends through non-conductive structure 214 to make contact with conductive structure 210. Conductive structure 210, in turn, can represent a silicon region, such as a source or drain region, a silicided region formed on silicon or polysilicon, or a metal trace.
As further shown in FIGS. 2A-2C, switch 200 also includes a support layer 220 that touches the top surface of non-conductive structure 214 and via 216. Support layer 220, which is commonly implemented with nitride, includes an opening 222 that exposes the top surface of via 216. In addition, switch 200 further includes a carbon nanotube structure 224 that touches lower support layer 220 and extends across opening 222.
FIG. 2A illustrates via 216 with a substantially planar top surface and carbon nanotube structure 224 lying in the open switch position, while FIG. 2B illustrates via 216 with a substantially planar top surface and carbon nanotube structure 224 lying in the closed switch position. Thus, as shown in FIG. 2B, when switch 200 is closed, carbon nanotube structure 224 extends down to make a predictable and reliable electrical connection with the substantially planar top surface of via 216.
However, as shown in FIG. 2C, when via 216 suffers from coring, via 216 no longer has a substantially planar top surface, but instead has a cavity 226. As a result, when switch 200 is closed and carbon nanotube structure 224 extends down to via 216, carbon nanotube structure 224 touches only the edges of via 216 and, therefore, is no longer able to make a predictable and reliable electrical connection with via 216.
A number of solutions to the problem of via coring have been proposed. For example, U.S. Patent Application Publication 2009/0256217 discusses plating a material into the cavity, forming silicon in the cavity and thermally cycling the silicon to convert the silicon into a silicide, and forming a metal cap on top of the via through a damascene or a conventional metal process.
Although a number of solutions to the problem of via coring have been suggested, there remains a need for alternate approaches to forming a via with a substantially planar top surface.